In the solid state semiconductor device art a variety of electronic components may be formed both within and on the surface of a semiconductor wafer. For example, resistors, diodes, transistors and thyristors may be fabricated and interconnected to form an integrated circuit by processing that includes appropriately doping various portions of the wafer. Additionally, a variety of differently structured conductor lines, resistors and capacitors may be formed on the surface of each device on the wafer. Due to the large number of processing steps and wide range of processing variables encountered during the fabrication of a conventional device, it has become a practical necessity to incorporate a variety of test structures on the wafer, to facilitate both the monitoring of the process and the testing of completed wafers.
In a conventional configuration, a plurality of test structures are used. For example, for each differently doped region on a device there is typically one test structure for measuring sheet resistance and one or two test structures for measuring line width. Each sheet resistance test structure typically includes four electrode contacts and four bond pads and the line width test structure(s) typically includes at least three additional electrode contacts and at least three more bond pads. For semiconductor device regions which are to be contacted by metallization on the wafer surface, there is additionally usually a similarly doped test structure for measuring contact resistance that may incorporate still additional electrode contacts and bond pads.
In a conventional semiconductor device manufacturing process, a rectangular array of devices, commonly referred to as chips, is formed on the surface of a semiconductor wafer, and the test structures are formed in what are termed knockout areas, i.e., areas which would otherwise be devices. As device structures become more complicated, it becomes necessary to incorporate a greater number of test structures within each knockout area. However, as the number of test structures is increased, the constraint imposed by the area of the knockout becomes a significant limitation and can ultimately reduce the number of measurable device parameters. In an effort to increase the amount of information which can be gleaned from a test structure of a given area, the present invention was conceived.